Many types of analog-to-digital converters, digital-to-analog converters, interleaved sampling circuits, serial links and other electronic circuits operate in response to interleaved clock signals. Accordingly, such circuits typically include an interleaved clock generator, or receive interleaved clock signals from an interleaved clock generator.
An interleaved clock generator receives an input clock signal and, in response to the input clock signal, generates a set of N interleaved clock signals. The interleaved clock signals have edges that are temporally equally spaced within the time period of one of the interleaved clock signals. Important design variables for an interleaved clock generator include the number of interleaved clock signals (N) and the time delay (Td) between corresponding edges of adjacent ones of the interleaved clock signals. For example, the time delay Td is the time delay between the positive-going edges of adjacent interleaved clock signals p and p+1, where 1≦p≦N−1.
FIG. 1A is a block diagram showing an example 10 of an interleaved clock generator that generates four interleaved clock signals, i.e., N=4 in the example shown. The interleaved clock generator 10 includes the clock input 12 and the four clock outputs 14-1, 14-2, 14-3 and 14-4 at which the interleaved clock signals K1, K2, K3 and K4, respectively, are output.
FIG. 1B shows the waveforms of the interleaved clock signals K1, K2, K3 and K4. The positive-going edges of all four interleaved clock signal waveforms are temporally equally spaced within the period of the interleaved clock signals, e.g., over the period t of the interleaved clock signal K1. The time delay between the positive-going edges of the waveforms of the adjacent interleaved clock signals K1 and K2 is indicated as Td.
Desirable performance characteristics of the interleaved clock generator 10 include that the interleaved clock generator generate a large number N of interleaved clock signals with a small time delay Td between corresponding edges of adjacent ones of the interleaved clock signals, and that the interleaved clock signals have small timing errors and low jitter. Timing errors include fixed timing offsets and cycle-to-cycle mismatches. Timing offsets are typically caused by mismatches between the stages of the interleaved clock generator that generate the individual interleaved clock signals. Cycle-to-cycle mismatches are typically caused by noise. Sources of noise include thermal noise in the interleaved clock generator and noise received from external sources, such as noise from a noisy power supply. Generally, the magnitude of the timing errors depends on the number of stages through which the input clock signal propagates to generate each individual interleaved clock signal.
Many conventional interleaved clock generators incorporate a ring counter. Other conventional interleaved clock generators incorporate a multi-stage serial-delay circuit. FIG. 2A is a block diagram of an example of a conventional interleaved clock generator 10 based exclusively on a ring counter 20. In the example shown, the ring counter is composed of four stages. Each of the four stages generates one of the four interleaved clock signals K1-K4 in response to the input clock signal K0.
The four-stage ring counter 20 is composed of the four stages 22-1, 22-2, 22-3 and 22-4. Each of the stages includes a data input D, a clock input CK and a data output Q. The data output of each stage 22-1 to 22-4 provides one of the interleaved clock signals K1-K4, respectively, and is connected to the respective one of the clock outputs 14-1 to 14-4 of the interleaved clock generator 10. The data output of each of the stages 22-1, 22-2 and 22-3 is additionally connected to the data input of the stages 22-2, 22-3 and 22-4, respectively. The data output of the stage 22-4 provides the interleaved clock signal K4 and is additionally connected to the data input of the stage 22-1. The clock input CK of each of the stages is connected to the input clock input 12.
Each of the stages 22-1 to 22-4 is configured such that the state of its data output Q is set to a predetermined state when power is applied. For example, each stage may additionally include a present input (not shown) connected to a preset line (not shown) that is asserted at power on to set the state of the data output to the predetermined state.
FIG. 2B shows waveforms of the input clock signal K0 and of the interleaved clock signals K1-K4 in an example of a conventional interleaved clock generator based exclusively on the ring counter 20. The interleaved clock signals K1-K4 are output by the stages 22-1 to 22-4, respectively. In the example shown, the output of one of the stages is preset to a 1 (high) state and the outputs of the remaining stages are preset to a 0 (low) state at power on. However, this is not critical: the outputs of the stages may be preset to any state provided that the outputs of a contiguous block composed of at least one of the stages differ in state from those of the remaining stages.
On each positive-going edge of the input clock signal K0 received at the input clock input 12, each of the stages 22-1 to 22-4 sets the state of its data output Q to the state present at its data input D. FIG. 2B shows an example in which the data output of stage 22-1 is preset to a 1 state and the data outputs of stages 22-2 to 22-4 are preset to a 0 state at power on. The 0 state output by stage 22-4 is present at the input of stage 22-1. The next positive-going edge of the input clock signal, shown at 31, sets the output of stage 22-1 (interleaved clock signal K1) to a 0 state, as shown at 32. Moreover, the positive-going edge of the input clock signal sets the output of stage 22-2 (interleaved clock signal K2) to a 1 state, as shown at 33, as a result of presence of the 1 state output by stage 22-1 at the input of stage 22-2. Corresponding changes occur in the outputs of stages 22-2 and 22-3, 22-3 and 22-4, and 22-4 and 22-1 on the positive-going edges 34, 35 and 36, respectively, of the input clock signal. Positive-going edge 36 restores the outputs of the stages to their original state that existed between power-on and positive-going edge 31, and the above-described sequence repeats.
In a ring counter-based interleaved clock generator, such as that shown in FIG. 2A, the frequency of the input clock signal K0 is 1/Td, where Td is the desired time delay between corresponding edges of adjacent ones of the interleaved clock signals K1-KN, and the frequency of each of the interleaved clock signals K0 is 1/(Td*N). Consequently, in a ring counter-based interleaved clock generator that generates N interleaved clock signals, the frequency of the input clock signal is N times that of the interleaved clock signals.
The interleaved clock generator based on the ring counter 20 has a number of practical advantages. The circuit from the input clock input 12 to each of the clock outputs 14-1 to 14-4 can be made similar for each of the clock outputs. The circuit from the clock input 12 to each of the clock outputs 14-1 to 14-4 can also be designed for minimum delay. These measures minimize timing errors and jitter in the interleaved clock signals K1-K4.
However, in an interleaved clock generator, the desired time delay Td and the number N of interleaved clock signals depends on the requirements of the circuit to which the interleaved clock signals are supplied. Current trends are towards reducing the time delay and increasing the number of interleaved clock signals. In an interleaved clock generator based on the ring counter 20, these trends significantly and the above-described input clock frequency multiplication factor significantly increase the frequency of the input clock signal. A very high input clock signal frequency makes it difficult both to design the input clock signal generator and to propagate the input clock signal from the input clock signal generator to the ring counter. The maximum frequency of the input clock signal that can be generated for a given power consumption by an input clock signal generator having a given circuit configuration and device feature size limits the maximum frequency of the input clock signal and, hence, imposes a practical minimum on the time delay Td. This minimum can be greater than the time delay required in modern applications.
FIG. 3A is a block diagram of an example of a conventional interleaved clock generator 10 based exclusively on a multi-stage serial-delay circuit 40. In the example shown, the multi-stage serial-delay circuit is composed of four delay stages. Each of the four delay stages generates one of the four interleaved clock signals K1-K4. The circuit operates in response to the input clock signal K0.
The four-stage serial-delay circuit 40 is composed of the four delay stages 42-1, 42-2, 42-3 and 42-4 connected in series. Each of the delay stages includes a data input D and a data output Q. The data output of each of the delay stages 42-1, 42-2, 42-3 and 42-4 provides one of the interleaved clock signals K1, K2, K3, and K4, respectively, and is connected to the respective one of the clock outputs 14-1, 14-2, 14-3 and 14-4. The data output of each of the delay stages 42-1, 42-2 and 42-3 is additionally connected to the data input D of the delay stages 42-2, 42-3 and 42-4, respectively. The data input D of the delay stage 42-1 is connected to the input clock input 12.
Each of the delay stages 42-1 to 42-4 outputs a signal received at its data input with a time delay substantially equal to the desired time delay Td. As will be described in more detail below, the four-stage serial-delay circuit 40 typically additionally includes a Delay Locked Loop (DLL) or a Phase Locked Loop (PLL) that controls the time delay of the delay stages to make the time delay equal the desired time delay Td. The open-loop embodiment shown in FIG. 3A is suitable for use in some applications in which the relative timing of the interleaved clock signals is less critical.
FIG. 3B shows waveforms of the input clock signal K0 and of the interleaved clock signals K1, K2, K3 and K4 in an example of a conventional ring counter based exclusively on the multi-stage serial delay circuit 40. The interleaved clock signals K1-K4 are output by the delay stages 42-1 to 42-4, respectively. Each of the interleaved clock signals K1-K4 has the same period as the input clock signal K0. The interleaved clock signal generated by the delay stage n is incrementally delayed relative to the interleaved clock signal generated by the delay stage n−1 by the time delay of the delay stage n. The time delays imposed by the delay stages 42-1, 42-2, 42-3 and 42-4 are indicated by Td1, Td2, Td3 and Td4, respectively. For example, the positive-going edge 51 of the interleaved clock signal K3 generated by the delay stage 42-3 is incrementally delayed relative to the positive-going edge 52 of the interleaved clock signal K2 generated by the delay stage 42-2 by the time delay Td3 of the delay stage 42-3.
The multi-stage serial-delay circuit 40 has a number of advantages. The minimum delay time of the delay stages 42-1 to 42-4 determines the minimum time delay Td. Moreover, the period of the input clock signal K0 and of the signals at any location in the multi-stage serial-delay circuit is about N×Td. Thus, the maximum frequency in the multi-stage serial-delay circuit is about the same as the frequency of the interleaved clock signals K1-KN. This substantially simplifies the frequency aspects of the circuit design compared with those of a ring counter-based interleaved clock generator configured to generate interleaved clock signals of the same frequency.
However, the multi-stage serial-delay circuit 40 suffers from the significant disadvantage that the input clock signal K0 must propagate through an average of N/2 delay stages, and a maximum of N delay stages, to reach the clock outputs 14-1 to 14-4. This can cause large timing errors and jitter, especially when N is large.
The number of delay stages through which the edges of the input clock signal propagate may be halved by halving the number of delay stages, using differential delay stages as the delay stages and using differential clock signals having a 50% duty cycle as the input clock signal K0. Then, the normal clock signals generated by the N/2 delay stages provide interleaved clock signals 1 to N/2, and the inverted interleaved clock signals generated by the N/2 delay stages provide interleaved clock signals ((N/2)+1) to N. This measure reduces the number of delay stages through which the input clock signal propagates by a factor of 2, but may still result in unacceptably-large timing errors and jitter.
Accordingly, what is needed is an interleaved clock generator that can generate a large number of interleaved clock signals that have the small timing errors and low jitter of interleaved clock signals generated by a ring counter but that are temporarily separated by a delay time that is less than that which can conveniently be provided by a ring counter. In other words, what is needed is an interleaved clock generator that can generate a large number of interleaved clock signals and that has an input clock signal requirement similar to that of a multi-stage serial-delay circuit but that does not suffer from the large timing errors and jitter that typically result from using a multi-stage serial-delay circuit to generate a large number of interleaved clock signals.